Printed circuit boards (PCB's) loaded with the components they were designed to carry are often tested for electrical integrity by using spring-loaded test pins that are vertically supported underneath a PCB under test (BUT) in position to contact the exposed nodes on the bottom surface of the BUT.
For example, Katz U.S. Pat. No. 4,132,948 discloses mounting test pins in an unloaded PCB having an identical hole pattern to that of the BUT so that the test pins automatically line up with the nodes being contacted. The test pins are directly connected to wires that are connected via cable assemblies to the test circuitry. When the circuit board tester is to be used to test PCB's having a different node pattern, the test pin support board is replaced with one having test pins corresponding to the node locations for the new PCB design.
Published European Patent Application No. 0 115 135 discloses a test fixture including a permanent base sheet carrying a large number of test pins and a lower customizing board that carries inserts that activate test pins at selected locations to be raised into activated position to contact nodes of a BUT. When used with a different BUT, a new customizing board, having inserts in the same pattern as that of the nodes of the new BUT, is installed. Underneath the customizing board, wire wrap post extensions of the inserts are wired to terminals at the side of the customizing board, for connection to test circuitry.
Published European Patent Application No. 0 050 913 discloses a test fixture including a general purpose platform that carries test pins in a uniform grid pattern and a backing plate that carries removable displacement modules that activate test pins at selected locations to contact nodes of a BUT. On the other side of the backing plate are wire wrap posts that are electrically connected to the test pins through the modules and are wired to a multiple pin plug at the edge of the backing plate.
In some prior art test systems channel circuit boards containing instruments for providing test signals to the BUT's and receiving resulting outputs were physically located underneath the test pins to reduce the distance between the instruments and the BUT to reduce distortions to test signals and outputs. In such systems there were a plurality of upwardly directed channel nodes at connectors at the upper ends of a plurality of channel boards (also referred to as channel cards), the channel nodes being electrically connected by wires to respective test pins carried on a test pin support board like that shown in Katz U.S. Pat. No. 4,132,948. The test pins were wired to upwardly directed right angle posts on small boards, the lower plated edges of which were in turn connected to zero-insertion force edge card connectors mounted on the channel cards. Before making the wire wrap connection to the right angle posts, the small boards carrying them were removed and turned upside down so that the posts were directed downward, the same direction as lower extensions of the test pins, to facilitate wire wrapping, and after wire wrapping, the small boards were rotated back and mounted in the edge card connectors with the wires folded over. In these systems, when a particular automatic tester was used with different types of BUT's having nodes at different locations, new test pin support boards were installed. A particular model automatic tester could be provided with different channel boards having different instrumentation, depending on the type of BUTs to be tested, and a user might want to add or modify channel boards, with the result that there would be different channel nodes for the same model of tester, and possibly even the same machine at different times.
In another prior art system, dual-ended test pins mounted on a probe plate in one pattern were electrically connected to probes connected to test circuitry in another pattern below the probe plate by a translator board between the two carrying upwardly directed wire wrap posts in position to contact lower spring-biased contacts of the dual ended test pins, downward extending wire wrap posts in position to contact lower test circuitry probes, and wires between various wire wrap posts.